DASL is an IBM protocol which is based on 500 MHz serial links that are bundled into 4 Gbps logical ports. DASL is used by the IBM Rainier network processor (NP) and the IBM PRIZMA-EP switch chip. Normally, the NP is connected directly to the switch via the DASL interface. However, to allow compatibility with future IBM products, there is a desire to use Unilink as a backplane interface.
Unilink protocol is based on Infiniband compliant 2.5 GHz serial links, using 8b/10b encoding and bundled into 16 Gbps logical ports (20 Gbps raw data rate with encoding). The EQ switch fabric uses Unilink as its interface. It allows the use of sub-ports, where backpressure information is gathered for four sub-ports in each logical port. This information is then broadcast to all other ports, allowing non-blocking backpressure to be applied to ports that are less than 16 G.
IBM provides a current solution which allows a Unilink backplane to connect to an EP switch fabric. This is known as the SCIC (Switch Core Interface Chip). The SCIC converts Unilink into DASL protocol on the switch card, and is designed to allow next generation line cards to communicate with the EP switch fabric. Next generation line cards will communicate with the switch through the C192 chip, which is a CSIX to Unilink converter. The C192 can communicate with both the SCIC and the EQ switch fabric, the EP switch chip is a currently used switch fabric which is a predecessor of EQ switch chip.
Unfortunately, there are several problems with the SCIC. First, it is not designed to interface to the NPs on the DASL side, as it only communicates with the EP switch fabric in a link parallel mode, where four 4 Gbps ports are logically connected to create a 16 Gbps port, thus making it impossible to connect four NPs to the DASL side. The second problem with the SCIC is that the data formats on the Unilink backplane are not compatible with data formats used by the EQ switch fabric. The C192 is designed to operate in two modes, the modes being SCIC or EQ. Third, the SCIC does not support the sub-port backpressure mechanism.
Currently, the only way to transfer information from the Rainier NPs to a Unilink backplane is to use an external programmable device (or several of them). This means that the FPGA chips must also have two modes, namely SCIC or EQ modes. In SCIC mode, there is no sub-port backpressure mechanism, so the four NPs connected through the FPGA to the SCIC must share a single port with only one backpressure mechanism. This means that each NP can block other processors. Additionally, it means that several different types of chips have to be used to achieve the required translation of signals between the two protocols. It makes electronic design extremely complicated and expensive.
Accordingly, there is a need in industry for development of an alternative solution, an interposer chip, which would avoid the above-mentioned problems.